Architecture Fundamentals
Category
12 articles
- 01CPUID
The instruction that reports which CPU features are actually present, letting software check before assuming.
- 02Debug Registers and Hardware Breakpoints
How a kernel programs DR0-DR3, DR7, and DR6 directly to implement its own memory watchpoints, without any external debugger involved.
- 03Hardware Random Number Generation (RDRAND/RDSEED)
Where a kernel gets real randomness with no input devices or network to draw entropy from, and why RDRAND and RDSEED answer two different questions.
- 04Long Mode
What changes when moving from 32-bit protected mode to 64-bit long mode.
- 05Model-Specific Registers
The RDMSR/WRMSR instructions and the per-core register space they access, separate from the CPU's ordinary general-purpose registers.
- 06Multiprocessor Bring-Up (SMP)
The INIT-SIPI-SIPI sequence the bootstrap processor uses to wake each additional CPU, the 16-bit trampoline it jumps into, and getting each core to its own stack.
- 07Port I/O versus Memory-Mapped I/O
The two separate ways x86 hardware talks to devices, and why most modern hardware picked one of them over the other.
- 08Protected Mode
Segmentation, the GDT, and how the CPU enforces privilege levels in 32-bit protected mode.
- 09The System V ABI and Calling Convention
Which registers carry a function's arguments and return value, stack alignment, and the red zone a leaf function can use without adjusting the stack.
- 10The Task State Segment
The structure the CPU reads to find a kernel stack on a privilege change, its I/O permission bitmap, and why SMP needs one per core.
- 11Unreal Mode
How a segment descriptor loaded through the GDT, without ever setting the protection-enable bit, leaves a 4 GB segment limit active back in real mode.
- 12x86 Architecture
The registers, modes, and privilege levels every x86 kernel has to work with.