Glossary

Definitions for terms used across this wiki, gathered in one place for quick lookup. Each entry links to the article covering it in full where one exists.

APIC: Advanced Programmable Interrupt Controller. The modern successor to the PIC, split into a per-CPU Local APIC and a shared I/O APIC, and required for interrupt delivery on any multiprocessor system.

BAR: Base Address Register. A PCI configuration space field through which a device reports the size and type of a memory or I/O region it needs.

Coalescing: In a heap allocator, merging a freed block with adjacent free blocks to counteract fragmentation.

Context switch: Saving one task’s CPU state and restoring another’s, the mechanism underlying multitasking.

CR3: The x86 control register holding the physical address of the currently active top-level page table.

Fragmentation: Memory wasted either inside an allocation (internal) or between allocations (external); see Heap Allocators.

GDT: Global Descriptor Table. Defines the memory segments and privilege levels available under protected and long mode.

IDT: Interrupt Descriptor Table. Maps each of 256 interrupt vectors to a handler address.

IRQ: Interrupt Request. A hardware interrupt line, historically 0–15 under the legacy PIC.

Long mode: x86-64’s 64-bit operating mode, requiring paging already active as a precondition of entry.

MMIO: Memory-Mapped I/O. Device registers exposed as ordinary memory addresses rather than through separate I/O ports.

MSR: Model-Specific Register. A CPU register accessed via RDMSR/WRMSR rather than a general-purpose register name, used for features such as syscall configuration and long mode’s enable bit.

MSI / MSI-X: Message Signaled Interrupts. A PCI mechanism delivering interrupts via memory writes rather than physical lines.

Page fault: The #PF exception raised when a memory access cannot be completed by the paging hardware alone.

PIC: Programmable Interrupt Controller. The legacy 8259 chip routing hardware interrupts to the CPU.

Preemption: A scheduler forcibly interrupting a running task, without its cooperation, typically via a timer; see Multitasking.

Ring: A privilege level (0 through 3) enforced by the CPU under protected and long mode; kernels run in ring 0, ordinary applications in ring 3.

TLB: Translation Lookaside Buffer. A CPU cache of recent virtual-to-physical address translations, avoiding a full page-table walk on every memory access.

VFS: Virtual Filesystem. A kernel layer exposing a uniform file interface over multiple underlying filesystem formats.